支持操作系统的额外指令
额外指令¶
算术指令：¶
clz: Count Leading Zeros in Word¶
| P102 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| clz | SPECIAL2 011100 | rs | rt | rd | 0 00000 | CLZ 100000 |
Bits 31..0 of GPR rs are scanned from most significant to least significant bit. The number of leading zeros is counted and the result is written to GPR rd.(detailed operation please refer to the document.)
clo: Count Leading Ones in Word¶
| P101 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| clo | SPECIAL2 011100 | rs | rt | rd | 0 00000 | CLZ 100001 |
Bits 31..0 of GPR rs are scanned from most significant to least significant bit. The number of leading ones is counted and the result is written to GPR rd.(detailed operation please refer to the document.)
乘法相关指令¶
mul: Multiply Word to GPR¶
| P189 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| mul | SPECIAL2 011100 | rs | rt | rd | 0 00000 | MUL 000010 |
Description: GPR[rd] ← GPR[rs] × GPR[rt]
The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The least significant 32 bits of the product are written to GPR rd. The contents of HI and LO are UNPREDICTABLE after the operation. No arithmetic exception occurs under any circumstances.
madd: Multiply and Add Word to Hi,Lo¶
| P160 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| madd | SPECIAL2 011100 | rs | rt | 0 00000 | 0 00000 | MADD 000000 |
Description: (HI,LO) ← (HI,LO) + (GPR[rs] × GPR[rt]) The 32-bit word value in GPR rs is multiplied by the 32-bit word value in GPR rt, treating both operands as signed values, to produce a 64-bit result. The product is added to the 64-bit concatenated values of HI and LO. The most significant 32 bits of the result are written into HI and the least signficant 32 bits are written into LO. No arithmetic exception occurs under any circumstances.
maddu: Multiply and Add Unsigned Word to Hi,Lo¶
| P162 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| maddu | SPECIAL2 011100 | rs | rt | 0 00000 | 0 00000 | MADDU 000001 |
Description: (HI,LO) ← (HI,LO) + (GPR[rs] × GPR[rt])
The 32-bit word value in GPR rs is multiplied by the 32-bit word value in GPR rt, treating both operands as unsigned values, to produce a 64-bit result.
msub: Multiply and Subtract Word to Hi,Lo¶
| P179 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| msub | SPECIAL2 011100 | rs | rt | 0 00000 | 0 00000 | MADDU 000100 |
Description: (HI,LO) ← (HI,LO) - (GPR[rs] × GPR[rt]) The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as signed values, to produce a 64-bit result.
msubu: Multiply and Subtract Word to Hi,Lo¶
| P181 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| msub | SPECIAL2 011100 | rs | rt | 0 00000 | 0 00000 | MADDU 000101 |
Description: (HI,LO) ← (HI,LO) - (GPR[rs] × GPR[rt]) The 32-bit word value in GPR rs is multiplied by the 32-bit value in GPR rt, treating both operands as usigned values, to produce a 64-bit result.
非对齐访存指令¶
lwl: Load Word Left¶
| P155 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| lwl | 100010 | base | rt | offset |
To load the most-significant part of a word as a signed value from an unaligned memory address Description: GPR[rt] ← GPR[rt] MERGE memory[GPR[base] + offset] The 16-bit signed offset is added to the contents of GPR base to form an effective address (EffAddr). EffAddr is the address of the most-significant of 4 consecutive bytes forming a word (W) in memory starting at an arbitrary byte boundary.
(detailed operation please refer to the document.)
lwr: load Word Right¶
| P157 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| lwl | 100110 | base | rt | offset |
To load the least-significant part of a word from an unaligned memory address as a signed value. Description: GPR[rt] ← GPR[rt] MERGE memory[GPR[base] + offset]
swl: Store Word Left¶
| P249 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| lwl | 101010 | base | rt | offset |
To store the most-significant part of a word to an unaligned memory address Description: memory[GPR[base] + offset] ← GPR[rt]
swr: Store Word Right¶
| P251 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| lwr | 101110 | base | rt | offset |
To store the least-significant part of a word to an unaligned memory address Description: memory[GPR[base] + offset] ← GPR[rt]
条件执行指令¶
movn: Move Conditional on Not Zero¶
| P173 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| movn | SPECIAL 000000 | rs | rt | rd | 0 00000 | MOVN 001011 |
Description: if GPR[rt] ≠ 0 then GPR[rd] ← GPR[rs] If the value in GPR rt is not equal to zero, then the contents of GPR rs are placed into GPR rd.
movz: Move Conditional on Zero¶
| P177 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| movz | SPECIAL 000000 | rs | rt | rd | 0 00000 | MOVN 001010 |
Description: if GPR[rt] = 0 then GPR[rd] ← GPR[rs] If the value in GPR rt is equal to zero, then the contents of GPR rs are placed into GPR rd.
TLB 类型指令¶
tlbp: Probe TLB for Matching Entry¶
| P268 | 31:26 | 25 | 24:6 | 5:0 |
|---|---|---|---|---|
| tlbp | COP0 010000 | CO 1 | 0 000 0000 0000 0000 0000 | TLBP 001000 |
Purpose: Probe TLB for Matching Entry. To find a matching entry in the TLB.
Description: The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register. If no TLB entry matches, the high-order bit of the Index register is set.
tlbr: Read Indexed TLB Entry¶
| P269 | 31:26 | 25 | 24:6 | 5:0 |
|---|---|---|---|---|
| tlbr | COP0 010000 | CO 1 | 0 000 0000 0000 0000 0000 | TLBR 000001 |
Purpose: Read Indexed TLB Entry. To read an entry from the TLB.
Description: The EntryHi, EntryLo0, EntryLo1, and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register.
tlbwi: Write Indexed TLB Entry¶
| P271 | 31:26 | 25 | 24:6 | 5:0 |
|---|---|---|---|---|
| tlbwi | COP0 010000 | CO 1 | 0 000 0000 0000 0000 0000 | TLBWI 000010 |
Purpose: Write Indexed TLB Entry. To write a TLB entry indexed by the Index register
Description: The TLB entry pointed to by the Index register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. It is implementation dependent whether multiple TLB matches are detected on a TLBWI
tlbwr(可不实现): Write Random TLB Entry¶
| P273 | 31:26 | 25 | 24:6 | 5:0 |
|---|---|---|---|---|
| tlbwi | COP0 010000 | CO 1 | 0 000 0000 0000 0000 0000 | TLBWI 000110 |
Purpose: Write Random TLB Entry. To write a TLB entry indexed by the Random register.
The TLB entry pointed to by the Random register is written from the contents of the EntryHi, EntryLo0, EntryLo1, and PageMask registers. It is implementation dependent whether multiple TLB matches are detected on a TLBWR.
Trap 类型指令¶
teq: Trap if Equal¶
| P262 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| teq | SPECIAL 000000 | rs | rt | code | TEQ 110100 |
Description: if GPR[rs] = GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is equal to GPR rt, then take a Trap exception.
teqi: Trap if Equal Immediate¶
| P263 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| teqi | REGIMM 000001 | rs | TEQI 01100 | immediate |
Description: if GPR[rs] = immediate then Trap Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is equal to immediate, then take a Trap exception.
tge: Trap if Greater or Equal¶
| P264 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| tge | SPECIAL 000000 | rs | rt | code | TGE 110000 |
Description: if GPR[rs] ≥ GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is equal to GPR rt, then take a Trap exception.
tgei: Trap if Greater or Equal Immediate¶
| P265 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| tgei | REGIMM 000001 | rs | TGEIU 01000 | immediate |
Description: if GPR[rs] ≥ immediate then Trap Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is equal to immediate, then take a Trap exception.
tgeiu: Trap if Greater or Equal Immediate Unsigned¶
| P266 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| tgeiu | REGIMM 000001 | rs | TGEIU 01001 | immediate |
Description: if GPR[rs] ≥ immediate then Trap Compare the contents of GPR rs and the 16-bit signed immediate as unsigned integers; if GPR rs is equal to immediate, then take a Trap exception.
tgeu: Trap if Greater or Equal Unsigned¶
| P267 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| tgeu | SPECIAL 000000 | rs | rt | code | TGEU 110001 |
Description: if GPR[rs] ≥ GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is greater than or equal to GPR rt, then take a Trap exception.
tlt: Trap if Less Than¶
| P274 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| tlt | SPECIAL 000000 | rs | rt | code | TLT 110010 |
Description: if GPR[rs] < GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is less than GPR rt, then take a Trap exception.
tlti: Trap if Less Than Immediate¶
| P275 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| tlti | REGIMM 000001 | rs | TLTI 01010 | immediate |
Description: if GPR[rs] < immediate then Trap Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is less than immediate, then take a Trap exception.
tltiu: Trap if Less Than Immediate Unsigned¶
| P275 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| tltiu | REGIMM 000001 | rs | TLTIU 01011 | immediate |
Description: if GPR[rs] < immediate then Trap Compare the contents of GPR rs and the 16-bit sign-extended immediate as unsigned integers; if GPR rs is less than immediate, then take a Trap exception.
tltu: Trap if Less Than Unsigned¶
| P277 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| tltu | SPECIAL 000000 | rs | rt | code | TLTU 110011 |
Description: if GPR[rs] < GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as unsigned integers; if GPR rs is less than GPR rt, then take a Trap exception.
tne: Trap if Not Equal¶
| P278 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| tne | SPECIAL 000000 | rs | rt | code | TNE 110110 |
Description: if GPR[rs] ≠ GPR[rt] then Trap Compare the contents of GPR rs and GPR rt as signed integers; if GPR rs is not equal to GPR rt, then take a Trap exception.
tnei: Trap if Not Equal Immediate¶
| P279 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| tnei | REGIMM 000001 | rs | TNEI 01110 | immediate |
Description: if GPR[rs] ≠ immediate then Trap Compare the contents of GPR rs and the 16-bit signed immediate as signed integers; if GPR rs is not equal to immediate, then take a Trap exception.
缓存相关指令¶
cache: Perform Cache Operation¶
| P91 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| cache | 101111 | base | op | offset |
Description: The 16-bit offset is sign-extended and added to the contents of the base register to form an effective address. The effective address is used in one of the following ways based on the operation to be performed and the type of cache as described in the following table.(refer to the document for details)
pref(可实现为nop): Prefetch¶
| P205 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| pref | 110011 | base | hint | offset |
Description: prefetch_memory(GPR[base] + offset) PREF adds the 16-bit signed offset to the contents of GPR base to form an effective byte address. The hint field supplies information about the way that the data is expected to be used.(refer to the document for details)
多核同步指令¶
ll(可实现为lw): Load Linked Word¶
| P149 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| ll | 110000 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset]
sc(可实现为sw): Store Conditional Word¶
| P149 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| sc | 111000 | base | rt | offset |
Description: if atomic_update then memory[GPR[base] + offset] ← GPR[rt], GPR[rt] ← 1 else GPR[rt] ← 0
sync(可实现为nop)¶
| P254 | 31:26 | 25:11 | 10:6 | 5:0 |
|---|---|---|---|---|
| sync | SPECIAL 000000 | 0 00 0000 0000 0000 0 | stype | SYNC 001111 |
Branch likely 指令¶
这部分指令可通过修改软件代码的方式去除
beql: Branch on Equal Likely¶
| P269 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| beql | 010100 | rs | rt | offset |
Description: if GPR[rs] = GPR[rt] then branch_likely An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
If the contents of GPR rs and GPR rt are equal, branch to the target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
bgezall: Branch on Greater Than or Equal to Zero and Link Likely¶
| P72 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bgezall | REGIMM 000001 | rs | BGEZALL 10011 | offset |
Purpose: Branch on Greater Than or Equal to Zero and Link Likely To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.
Description: if GPR[rs] ≥ 0 then procedure_call_likely
bgezl: Branch on Greater Than or Equal to Zero Likely¶
| P74 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bgezl | REGIMM 000001 | rs | BGEZL 00011 | offset |
Purpose: Branch on Greater Than or Equal to Zero Likely To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.
Description: if GPR[rs] ≥ 0 then branch_likely
bgtzl: Branch on Greater Than Zero Likely
| P76 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bgtzl | 010111 | rs | 0 00000 | offset |
Purpose: Branch on Greater Than Zero Likely To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if GPR[rs] > 0 then branch_likely
blezl: Branch on Less Than or Equal to Zero Likely¶
| P78 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| blezl | 010110 | rs | 0 00000 | offset |
Purpose: Branch on Less Than or Equal to Zero Likely To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if GPR[rs] ≤ 0 then branch_likely
bltzall: Branch on Less Than Zero and Link Likely¶
| P81 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bltzall | REGIMM 000001 | rs | BLTZALL 10010 | offset |
Purpose: Branch on Less Than Zero and Link Likely To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken. Description: if GPR[rs] < 0 then procedure_call_likely
btlzl: Branch on Less Than Zero Likely¶
| P83 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bltzl | REGIMM 000001 | rs | BLTZL 00010 | offset |
Purpose: Branch on Less Than Zero Likely To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if GPR[rs] < 0 then branch_likely
bnel: Branch on Not Equal Likely¶
| P85 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| bnel | 010101 | rs | rt | offset |
Purpose: Branch on Not Equal Likely To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Description: if GPR[rs] ≠ GPR[rt] then branch_likely
等待中断指令¶
wait¶
(可实现为阻塞所有流水线，只有中断使能为高时，才跳转到异常处理程序)
| P282 | 31:26 | 25 | 24:6 | 5:0 |
|---|---|---|---|---|
| wait | COP0 010000 | CO 1 | Implementation-dependent code | WAIT 100000 |
Purpose: Enter Standby Mode Wait for Event
The WAIT instruction is typically implemented by stalling the pipeline at the completion of the instruction and entering a lower power mode.