指令集
labs指令集¶
参考资料：Volume II_ MIPS32 Instruction Set
关于指令的详细内容请查阅上述资料
指令格式：
| 对应的页数 | 数据范围 |
|---|---|
| 指令名称 | 对应的寄存器或立即数等等信息 |
lab1 指令¶
addiu¶
| P48 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| ADDIU | 001001 | rs | rt | immediate |
Description: GPR[rt] ← GPR[rs] + immediate(signed) (No exception)
addu¶
| P49 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| ADDU | special 000000 | rs | rt | rd | 0 00000 | ADDU 100001 |
Description: GPR[rd] ← GPR[rs] + GPR[rt] (No exception)
and¶
| P52 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| AND | special 000000 | rs | rt | rd | 0 00000 | AND 100100 |
Description: GPR[rd] ← GPR[rs] AND GPR[rt]
andi¶
| P53 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| ANDI | 001100 | rs | rt | imme |
Description: GPR[rt] ← GPR[rs] AND immediate(zero-extended)
beq: Branch on Equal¶
| P68 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BEQ | 000100 | rs | rt | offset |
Description: if GPR[rs] = GPR[rt] then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself)
bne: Branch on Not Equal¶
| P84 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BNE | 000101 | rs | rt | offset |
Description: if GPR[rs] ≠ GPR[rt] then branch
j: Jump¶
| P129 | 31:26 | 25:0 |
|---|---|---|
| J | 000010 | instr_index |
Description: This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2 bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself, but they are same in most cases).
jal: Jump and Link¶
| P130 | 31:26 | 25:0 |
|---|---|---|
| JAL | 000011 | instr_index |
Description: Place the return address link in GPR 31(register). The return link is the address of the second instruction following the branch, at which location execution continues after a procedure call.
This is a PC-region branch (not PC-relative); the effective target address is in the “current” 256 MB-aligned region. The low 28 bits of the target address is the instr_index field shifted left 2bits. The remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself).
jr: Jump Register¶
| P138 | 31:26 | 25:21 | 20:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|
| JR | special 000000 | rs | 0 0000000000 | hint | JR 001000 |
Description: PC ← GPR[rs]
lui: Load Upper Immediate¶
| P150 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LUI | 001111 | 0 00000 | rt | imme |
Description: GPR[rt] ← immediate || 016
The 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order zeros.
lw: Load Word¶
| P152 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LW | 100011 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset(signed_extended)]
The 16-bit signed offset is added to the contents of GPR base to form the effective address.
nor¶
| P197 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| NOR | special 000000 | rs | rt | rd | 0 00000 | NOR 100111 |
Description: GPR[rd] ← GPR[rs] NOR GPR[rt]
or¶
| P197 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| OR | special 000000 | rs | rt | rd | 0 00000 | OR 100101 |
Description: GPR[rd] ← GPR[rs] or GPR[rt]
ori: Or Immediate¶
| P199 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| ORI | 001101 | rs | rt | imme |
Description: GPR[rt] ← GPR[rs] or immediate(zero_extended)
sll: Shift Word Left Logical¶
| P230 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SLL | special 000000 | 0 00000 | rt | rd | sa | SLL 000000 |
Description: GPR[rd] ← GPR[rt] << sa
slt: Set on Less Than¶
| P232 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SLT | special 000000 | rs | rt | rd | 0 00000 | SLT 101010 |
Description: GPR[rd] ← (GPR[rs] < GPR[rt])
Compare the contents of GPR rs and GPR rt as signed integers.
slti: Set on Less Than Immediate¶
| P233 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| SLTI | 001010 | rs | rt | imme |
Description: GPR[rt] ← (GPR[rs] < immediate)
Compare the contents of GPR rs and the 16-bit signed immediate.
sltiu: Set on Less Than Immediate Unsigned¶
| P234 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| SLTIU | 001011 | rs | rt | imme |
Description: GPR[rt] ← (GPR[rs] < immediate)
Compare the contents of GPR rs and the sign-extended 16-bit immediate as unsigned integers.
sltu: Set on Less Than Unsigned¶
| P235 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SLTU | special 000000 | rs | rt | rd | 0 00000 | SLTU 101011 |
Description: GPR[rd] ← (GPR[rs] < GPR[rt])
Compare the contents of GPR rs and GPR rt as unsigned integers.
sra: Shift Word Right Arithmetic¶
| P237 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SRA | special 000000 | 0 00000 | rt | rd | sa | SRA 000011 |
Description: GPR[rd] ← GPR[rt] >> sa (arithmetic)
The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits.
srl: Shift Word Right Logical
| P239 | 31:26 | 25:22 | 21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|---|
| SRL | special 000000 | 0 0000 | R 0 | rt | rd | sa | SRL 000010 |
Description: GPR[rd] ← GPR[rt] >> sa (logical)
The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits.
subu¶
| P244 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SUBU | special 000000 | rs | rt | rd | 0 00000 | SUBU 100011 |
Description: GPR[rd] ← GPR[rs] − GPR[rt] (Unsigened, No exceptions)
sw¶
| P246 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| SW | 101011 | base | rt | offset |
Description: memory[GPR[base] + offset(sign_extended)] ← GPR[rt]
The least-significant 32-bit word of GPR rt is stored in memory
xor¶
| P285 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| XOR | special 000000 | rs | rt | rd | 0 00000 | XOR 100110 |
Description: GPR[rd] ← GPR[rs] XOR GPR[rt]
xori¶
| P286 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| XORI | 001110 | rs | rt | imme |
Description: GPR[rt] ← GPR[rs] XOR immediate
Combine the contents of GPR rs and the 16-bit zero-extended immediate.
lab2 指令¶
bgez, bgezal, blez, bgtz, bltz, bltzal, jalr, lb, lbu, lh, lhu, sb, sh, sllv, srav, srlv,
bgez: Branch on Greater Than or Equal to Zero¶
| P70 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BGEZ | REGIMM 000001 | rs | BGEZ 00001 | offset |
Description: if GPR[rs] ≥ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself),
bgezal: Branch on Greater Than or Equal to Zero and Link¶
| P71 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BGEZAL | REGIMM 000001 | rs | BGEZAL 10001 | offset |
Description: if GPR[rs] ≥ 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch,
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself)
bgtz: Branch on Greater Than Zero¶
| P75 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BGTZ | 000111 | rs | 0 00000 | offset |
Description: if GPR[rs] > 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself)
blez: Branch on Less Than or Equal to Zero¶
| P77 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BLEZ | 000110 | rs | 0 00000 | offset |
Description: if GPR[rs] ≤ 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself),
bltz: Branch on Less Than Zero¶
| P79 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BLTZ | REGIMM 000001 | rs | BLTZ 00000 | offset |
Description: if GPR[rs] < 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself),
bltzal: Branch on Less Than Zero and Link¶
| P80 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| BLTZAL | REGIMM 000001 | rs | BLTZAL 10010 | offset |
Description: if GPR[rs] < 0 then procedure_call
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself)
jalr: Jump and Link Register¶
| P131 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| JALR | special 000000 | rs | 0 00000 | rd | hint | JALR 001001 |
Description: GPR[rd] ← return_addr, PC ← GPR[rs] Place the return address link in GPR rd. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.
lb¶
| P142 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LB(load byte) | 100000 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset] The contents of the 8-bit byte at the memory location specified by the effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
lbu¶
| P143 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LBU(load byte unsigned) | 100100 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset] The contents of the 8-bit byte at the memory location specified by the effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
lh¶
| P147 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LH(load halfword) | 100001 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset] The contents of the 16-bit halfword at the memory location specified by the aligned effective address are fetched, sign-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
lhu¶
| P148 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| LHU(load halfword unsigned) | 100101 | base | rt | offset |
Description: GPR[rt] ← memory[GPR[base] + offset] The contents of the 16-bit halfword at the memory location specified by the aligned effective address are fetched, zero-extended, and placed in GPR rt. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
sb¶
| P220 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| SB(Store Byte) | 101000 | base | rt | offset |
Description: memory[GPR[base] + offset] ← GPR[rt] The least-significant 8-bit byte of GPR rt is stored in memory at the location specified by the effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
sh¶
| P229 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| SH(Store Halfword) | 101001 | base | rt | offset |
Description: memory[GPR[base] + offset] ← GPR[rt] The least-significant 16-bit halfword of register rt is stored in memory at the location specified by the aligned effective address. The 16-bit signed offset is added to the contents of GPR base to form the effective address.
sllv: Shift Word Left Logical Variable¶
| P231 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SLLV | special 000000 | rs | rt | rd | 0 00000 | SLLV 000100 |
Description: GPR[rd] ← GPR[rt] << rs The contents of the low-order 32-bit word of GPR rt are shifted left, inserting zeros into the emptied bits; the result word is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs.
srav: Shift Word Right Arithmetic Variable¶
| P238 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SRAV | special 000000 | rs | rt | rd | 0 00000 | SRAV 000111 |
Description: GPR[rd] ← GPR[rt] >> GPR[rs] (the description in document is wrong, you can refer to the following "Operation") The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs.
srlv: Shift Word Right Logical Variable¶
| P240 | 31:26 | 25:21 | 20:16 | 15:11 | 10:7 | 6 | 5:0 |
|---|---|---|---|---|---|---|---|
| SRLV | special 000000 | rs | rt | rd | 0000 | R 0 | SRLV 000110 |
Description: GPR[rd] ← GPR[rt] >> GPR[rs] (logical) The contents of the low-order 32-bit word of GPR rt are shifted right, inserting zeros into the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs.
lab3 指令¶
test3: div, divu, mfhi, mflo, mthi, mtlo, mult, multu
div¶
| P116 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| DIV | special 000000 | rs | rt | 0 00 0000 0000 | DIV 011010 |
Description: (HI, LO) ← GPR[rs] / GPR[rt] The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as signed values. The 32-bit quotient is placed into special register LO and the 32-bit remainder isplaced into special register HI. No arithmetic exception occurs under any circumstances.
divu¶
| P119 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| DIVU | special 000000 | rs | rt | 0 00 0000 0000 | DIVU 011011 |
Description: (HI, LO) ← GPR[rs] / GPR[rt] The 32-bit word value in GPR rs is divided by the 32-bit value in GPR rt, treating both operands as unsigned values. The 32-bit quotient is placed into special register LO and the 32-bit remainder is placed into special register HI.
No arithmetic exception occurs under any circumstances.
mfhi: Move From HI Register¶
| P168 | 31:26 | 25:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|
| MFHI | special 000000 | 0 00 0000 0000 | rd | 0 00000 | MFHI 010000 |
Description: GPR[rd] ← HI The contents of special register HI are loaded into GPR rd.
mflo: Move From LO Register¶
| P169 | 31:26 | 25:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|
| MFLO | special 000000 | 0 00 0000 0000 | rd | 0 00000 | MFLO 010010 |
Description: GPR[rd] ← LO The contents of special register LO are loaded into GPR rd.
mthi: Move to HI Register¶
| P187 | 31:26 | 25:21 | 20:6 | 5:0 |
|---|---|---|---|---|
| MTHI | special 000000 | rs | 0 000 0000 0000 0000 | MTHI 010001 |
Description: HI ← GPR[rs] The contents of GPR rs are loaded into special register HI.
mtlo: Move to LO Register¶
| P188 | 31:26 | 25:21 | 20:6 | 5:0 |
|---|---|---|---|---|
| MTLO | special 000000 | rs | 0 000 0000 0000 0000 | MTLO 010011 |
Description: LO ← GPR[rs] The contents of GPR rs are loaded into special register LO.
mult¶
| P191 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| MULT | special 000000 | rs | rt | 0 00 0000 0000 | MULT 011000 |
Description: (HI, LO) ← GPR[rs] × GPR[rt] The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the highorder 32-bit word is splaced into special register HI. No arithmetic exception occurs under any circumstances.
multu¶
| P192 | 31:26 | 25:21 | 20:16 | 15:6 | 5:0 |
|---|---|---|---|---|---|
| MULTU | special 000000 | rs | rt | 0 00 0000 0000 | MULTU 011001 |
Description: (HI, LO) ← GPR[rs] × GPR[rt]
The 32-bit word value in GPR rt is multiplied by the 32-bit value in GPR rs, treating both operands as signed values, to produce a 64-bit result. The low-order 32-bit word of the result is placed into special register LO, and the highorder 32-bit word is splaced into special register HI. No arithmetic exception occurs under any circumstances.
lab4 指令¶
add¶
| P45 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| ADD | special 000000 | rs | rt | rd | 0 00000 | ADD 100000 |
Description: GPR[rd] ← GPR[rs] + GPR[rt] (exception occurs if overflow)
- If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
addi¶
| P47 | 31:26 | 25:21 | 20:16 | 15:0 |
|---|---|---|---|---|
| ADDI | 001000 | rs | rt | immediate |
Description: GPR[rt] ← GPR[rs] + immediate(To add a constant to a 32-bit integer. If overflow occurs, then trap.)
- The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
sub¶
| P242 | 31:26 | 25:21 | 20:16 | 15:11 | 10:6 | 5:0 |
|---|---|---|---|---|---|---|
| SUB | SPECIAL 000000 | rs | rt | rd | 0 00000 | SUB 100010 |
Description: GPR[rd] ← GPR[rs] − GPR[rt] The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs to produce a 32-bit result. If the subtraction results in 32-bit 2’s complement arithmetic overflow, then the destination register is not modified and an Integer Overflow exception occurs. If it does not overflow, the 32-bit result is placed into GPR rd.
eret: Exception Return¶
| P122 | 31:26 | 25:24 | 24: 6 | 5:0 |
|---|---|---|---|---|
| ERET | COP0 010000 | CO 1 | 0 000 0000 0000 0000 0000 | ERET 011000 |
Description: ERET clears execution and instruction hazards, conditionally restores $SRSCtl_{CSS}$ from $SRSCtl_{ΠΣΣ}$ in a Release 2 implementation, and returns to the interrupted instruction at the completion of interrupt, exception, or error processing. ERET does not execute the next instruction (i.e., it has no delay slot).
mfc0: Move from Coprocessor 0¶
| P163 | 31:26 | 25:21 | 20:16 | 15:11 | 10:3 | 2:0 |
|---|---|---|---|---|---|---|
| MFC0 | COP0 010000 | MF 00000 | rt | rd | 0 00000000 | sel |
Description: GPR[rt] ← CPR[0,rd,sel] The contents of the coprocessor 0 register specified by the combination of rd and sel are loaded into general register rt. Note that not all coprocessor 0 registers support the sel field. In those instances, the sel field must be zero.reference.
mtc0: Move to Coprocessor 0¶
| P182 | 31:26 | 25:21 | 20:16 | 15:11 | 10:3 | 2:0 |
|---|---|---|---|---|---|---|
| MTC0 | COP0 010000 | MT 00100 | rt | rd | 0 00000000 | sel |
Description: CPR[0, rd, sel] ← GPR[rt] The contents of general register rt are loaded into the coprocessor 0 register specified by the combination of rd andsel. Not all coprocessor 0 registers support the the sel field. In those instances, the sel field must be set to zero.
break¶
| P86 | 31:26 | 25:6 | 5:0 |
|---|---|---|---|
| BREAK | SPECIAL 000000 | code | BREAK 001101 |
Description: A breakpoint exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
syscall¶
| P261 | 31:26 | 25:6 | 5:0 |
|---|---|---|---|
| SYSCALL | SPECIAL 000000 | code | SYSCALL 001100 |
Description: A system call exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.